1. Field of the Invention
The present invention relates to memory elements, and in particular to an apparatus and a method for optimizing the functioning of memory elements, and to DRAM memory devices using such an apparatus or such a method for optimizing their functioning.
2. Description of the Related Art
Today DRAM memory devices are employed in a multiplicity of electronic devices, with DRAM memory devices being used in particular as system memories or main memories of computer systems. In this, the DRAM memory devices play a very great role for the efficiency and stability of the computer systems.
DRAM memory devices (DRAM=dynamic random access memory) comprise a multiplicity of dynamic memory cells that are generally very simply constructed. A dynamic memory cell often consists of a selection transistor controllable via a word line and a storage capacitor readable and writeable via a bit line. The memory states “0” and “1” of the memory cell correspond to the positive and negative charge state of the storage capacitor, respectively. Since the capacitor charge in the memory cells decays within a relatively short period of time owing to recombination processes and leakage currents, the capacitor charge always has to be refreshed again in so-called refresh cycles. After a read operation information also has to be written into the memory cell again. The refresh operation takes places automatically with the analog image data of a circuit integrated on the memory device.
Because of its simple construction, the dynamic memory cell is also very inexpensive for DRAM memory devices. The working or mass memories of today's computers from the PC (personal computer) to the mainframe computer therefore mostly consist of DRAM memory devices.
According to the designation DRAM memory device (DRAM=dynamic random access memory), in a write-read memory, data may be arbitrarily stored and read out again in form of single bits or bit patterns. FIG. 4 now schematically shows an exemplary construction of a 64-bit memory element 400 with matrix-shaped arrangement of the DRAM memory cells 402 that may each accommodate a bit. In FIG. 4 the memory contents are entered in arbitrary distribution as “zeros” and “ones”. By means of a control logic circuit 412, a row and column decoder 408, 410 and a sense amplifier 414, the memory cells 402 may be addressed individually with an address A0, A1, . . . An via word lines 404 (x0–x7) and bit lines 406 (BL0–BL7) operative as row and column activation lines. It should be noted that the circuit block 414 designated as sense amplifier further comprises an input/output controller for associating a data stream with reference to the individual memory cells 402, wherein this circuit block consisting of sense amplifier and input/output controller is further designated as sense amplifier 414 for simplification of the further description.
In the construction illustrated in FIG. 4 of a known DRAM memory device 400, the sense amplifier 414 is controlled by the column decoder 410 via the lines 416 (y1–y7) and by the control logic circuit 412 to adjust the write or read operation of the sense amplifier 414 with reference to the individual bit lines 406.
As can further be seen from FIG. 4, the DRAM memory cells 402 comprise two main components, namely a storage capacitor 402a storing charge and an access transistor 402b transferring the charge into the storage capacitor 402a and out of it.
In order to now write data into the memory cell 402, a predetermined voltage is applied to the corresponding word line 404 (x0–x7) so that the access transistor 402b connected to this word line 404 becomes conducting. With this, the charge supplied through the associated bit line 406 is written into the storage capacitor 402a. 
In reading data a predetermined voltage is again applied to the word line 404 to connect the access transistor 402b through, so that the charge stored in the storage capacitor 402a may be read out on the associated bit line 406.
Via the control logic means 412, the DRAM memory device 400 may selectively be adjusted to write or read operation. The addressed memory cell 402 may be written with a “1” or a “0” via bit lines 406. At the output Q of the sense amplifier 414 (consisting of sense amplifier and input/output controller) connected to the individual memory cells 402 via the bit lines 406, the content of the memory cells 402 is readable. The input signals of the control logic means 412 are explained in even greater detail in the following on the basis of FIG. 5.
It should be noted that individual circuit parts, such as the control logic means 412, may be implemented differently in the individual case depending on technology, e.g. in BiCMOS or CMOS technology.
An important parameter for the characterization of the efficiency of such a DRAM memory device 400 represents its “access time” also designated as maximum access time. The access time is, according to definition, the time span between the instant of applying the address of the memory cell 402 and the instant of the appearing of the stored data at the output Q of the memory device 400. The access time is substantially due to device-internal signal runtimes and is held to be the characteristic quantity of a DRAM memory device.
FIG. 5 now schematically shows a time diagram for a typical access cycle of a DRAM memory device. In the timing diagram of FIG. 5, the instants t1–t5 indicating the execution instants of various operations of the DRAM memory element are illustrated in a purely schematic manner. The illustrated instants t1–t5 are only intended to serve for the fundamental explanation of the course of a DRAM access cycle and not to illustrate actual size ratios.
In a DRAM access cycle, substantially the following main operations exist. At the instant t1 the DRAM memory cell begins with the execution of a row active operation. At the instant t2, the DRAM memory cell begins executing a read/write command, i.e. a system memory control unit sends a read/write command to the DRAM memory cell. At the instant t3, the DRAM memory cell sends the required data outside. At the instant t4, the DRAM memory cell begins executing the preload operation. At the instant t5, the DRAM memory cell for example executes the row active operation for the next access cycle to the DRAM memory cell.
These parameters are fixedly default by the circuit layout and the production process of the memory element 400.
With respect to the time diagram schematically illustrated in FIG. 5, various time intervals between the execution instants of various operations of the memory device are defined as follows, wherein these time intervals are also designated in the following as timing parameters of the DRAM memory devices. The time intervals may for example be related to the system clock CK of the memory element 400.
The time interval between the beginning of an execution of a row active operation and the beginning of an execution of a read/write command is designated as the time interval TRCD and indicates the delay between a row address activation impulse (RAS) at the instant t1 and a column address activation impulse (CAS) at the instant t2, i.e. the time duration TRCD=t2−t1. The time interval TRCD thus represents one of the substantial timing parameters of DRAM memory devices, because the temporal distance between the activation of a word line (ACTIVE) and the subsequent read or write access command (READ or WRITE operation) of the memory cell is determined.
The refresh interval is indirectly dependent on the timing parameter TRCD, wherein according to the refresh interval each DRAM memory cell has to be refreshed to be brought to its full voltage value again. The retention time of a DRAM memory element now indicates the time span across which the DRAM memory cells can hold enough charge so that a correct read operation is possible. So the refresh interval is default by the retention time of a DRAM memory element.
The clock number during the time interval starting from the sending of a read command at the instant t2 to the DRAM memory cell until the outputting of the required data at the instant t3 from the DRAM memory cell is defined as CAS latency time and is designated as the time duration TCL=t3−t2.
The time interval from the beginning of a row active operation at the instant t1 until the beginning of a preload operation at the instant t4 is defined as the RAS impulse width time and is designated as the time interval TRAS. The time interval TRAS thus determines the temporal distance between the activation of a word line (ACTIVE operation) and the deactivation of this word line (PRECHARGE operation). The time interval TRAS is thus strongly linked to the timing parameters TRCD and TRP.
The time interval measured from the beginning of a precharge operation at the instant t4 until the beginning of the next row active operation at the instant t5 is defined as row precharge time and is designated as the time interval TRP. The TRP time interval thus determines the temporal distance between the activation of a word line (PRECHARGE operation) and a subsequent activation of a word line (ACTIVE operation) in the same memory bank.
Since the above-described timing parameters possess decisive influence on the performance characteristics of DRAM memory cells, such as on the access times of DRAM memory devices, in the production of DRAM memory devices great efforts are made to adjust these timing parameters, TRCD, TRAS, TRP, TCL, . . . as optimally as possible to be able to correspondingly increase the efficiency of the DRAM memory devices and thus also the efficiency of the computer systems using these memory devices.
In order to obtain the optimum timing parameters, the optimally obtainable real timing parameters of a DRAM memory device are for example ascertained in a test mode of the memory element in order to then adapt the circuit layout of the memory device to the timing parameters deemed optimal. For this, in the prior art various test apparatuses with special check programs are provided.
Improved timing parameters are obtained by fixedly adjusting the desired timing parameters by means of a specially designed metal option so that the specially adjusted timing parameters are fixedly linked to the respective circuit layout of the memory device.
The circuit layout of a DRAM memory element for example comprises various metal planes with different potentials, e.g. supply voltages, ground potential, and optionally also intermediate potentials. By a change of the circuit layout of the DRAM memory element, a special, new, fixed wiring of certain circuit elements of the control logic means of the DRAM memory element that have an influence on a timing parameter with the various metal planes is produced to influence a certain timing parameter so as to obtain a suitably adjusted, new timing parameter. This procedure is generally designated as the use of a new metal reticle (Metall1, Metall2) for the DRAM memory element.
But since the production processes of semiconductor devices are subject to constant variations, corresponding changes and variations also constantly result for the optimum adjusting points of the explained timing parameters of the memory devices. In order to now react to such variations in the semiconductor production processes and to be able to compensate for these at least partially, in working with a new metal option, a new reticle for the semiconductor production process has to be written, wherein the hardware has to pass through diverse procedural machining steps. This may however require months until a semiconductor device is ready to go into mass production. This makes clear that with the previously used metal options it can be reacted to variations in the semiconductor production processes only with a very great time delay and high technical expenditure.
Due to the inevitable variations in the production processes of semiconductor memory devices it is, however, not possible to adjust the (instantaneously optimal) timing parameter exactly for the normal operation of the semiconductor device, because between a test operation mode during which the optimal timing parameters may be ascertained and the production of new hardware with optimized timing parameters, as it is explained above, a very long time elapses. Therefore the timing parameters generally no longer optimal, ascertained in the long passed test mode of the semiconductor device underlie the instantaneous operation of the semiconductor device.
In order for the functioning of the DRAM memory device not to be affected by the inevitably occurring variations of an operation parameter of the semiconductor memory device, certain “safety time reserves” are provided for the respective timing parameters to guarantee reliable operability of the semiconductor devices. If the safety time reserves for the timing parameters are adjusted too short to, for example, produce semiconductor memory devices with very short access times lying very close to the timing parameters ascertained in the test mode, in practice, however, a relatively high reject quota of defective semiconductor memory devices to be sorted out will result due to the inevitable variations in the semiconductor production processes. For this reason, the respective optimal timing parameters of a DRAM memory device may not exactly be realized in large batch production processes.
Summing up, it can thus be established that in the prior art it has previously been extremely expensive to account for changed timing parameters of the DRAM memory devices due to variations in the production processes, because the reaction time duration for performing adaptations of the circuit layout of memory devices may lie in the area of several months. For this reason, relatively great safety reserves for the timing parameters of memory devices are made to keep the reject quota of defective memory devices as low as possible. Furthermore, the establishment of a new circuit layout for memory devices adapted to production process variations is very expensive, because in general a new reticle has to be produced for each new circuit layout, and the semiconductor device has to pass through a multiplicity of procedural machining steps.